1. Field of the Invention
The present invention generally relates to circuits and more particularly to linear equalizer circuits.
2. Description of Related Art
Persons of ordinary skill in the art will understand the terms used in this disclosure, such as MOS (metal-oxide semiconductor) transistor, including NMOS (n-channel metal-oxide semiconductor) transistor and PMOS (p-channel metal-oxide semiconductor) , “gate,” “source,” “drain,” “saturation region,” as used in connection with a MOS transistor, and basic concepts for electronic circuits, such as: “voltage,” “current,” “trans-conductance,” “source degeneration,” “slew rate,” “self-biasing,” “differential,” “pseudo-differential,” “single-ended,” “common-source,” “impedance,” “gain,” “frequency response,” “zero,” “pole,” and “Bode plot.” Terms and basic concepts like these are apparent from prior art documents, e.g. text book such as “Design of Analog CMOS Integrated Circuits” by Behzad Razavi, McGraw-Hill (ISBN 0-07-118839-8), and thus will not be expressly defined or explained in detail herein.
A linear equalizer is an apparatus for amplifying an input signal to generate an output signal with a gain factor that is deliberately frequency dependent, so as to accommodate a dispersive property of the input signal. A linear equalizer of particular interest is one that provides a higher gain for a higher frequency component of the input signal than a lower frequency component of the input signal. As depicted in FIG. 1, a conventional prior art linear equalizer 100 comprises: a differential pair 120 comprising NMOS (which stands for n-channel metal oxide semiconductor transistor) transistors 121 and 122 configured in a common-source amplifier configuration for amplifying a differential input signal VI (which comprises two ends VI+ and VI−) into a differential output signal VO (which comprises two ends VO+ and VO− •); a load 110 comprising resistors 111 and 112 for providing termination for the differential output signal VO; a biasing network 140 comprising current sources 141 and 142 for providing biasing currents I1 and I2 for the differential pair 120; and a RC-degeneration network 130 comprising a resistor 131 and a capacitor 132 for providing source degeneration to the differential pair 120. Throughout this disclosure, VDD denotes a power supply node, and VSS denotes a ground node. As known to those of ordinary skill in the art, source degeneration of a common-source MOS amplifier reduces a gain of the common-source MOS amplifier, and greater impedance of the source degeneration network leads to greater gain reduction. Here, impedance of the RC-degeneration network 130 is frequency dependent and decreases as frequency increases; a lower frequency component of the input signal VI encounters lower impedance of RC-degeneration and thus less gain reduction, compared with a higher frequency component of the input signal VI; therefore, a higher gain is provided for the higher frequency component of the input signal VI than the lower frequency component of the input signal VI.
Although linear equalizer 100 fulfills the purpose of equalization by providing a higher gain for a higher frequency component of the input signal than for a lower frequency component of the input signal, the equalization is fulfilled by enforcing “more gain reduction” on the lower frequency component instead of “more gain enhancement” on the higher frequency component of the input signal. As a result, a higher degree of equalization requires a higher degree of gain reduction for the lower frequency component. Due to the gain reduction, a subsequent wide-band amplifier, which provides approximately the same gain to both the lower frequency component and the higher frequency component, is often needed to compensate for the gain reduction due to the RC-degeneration.